1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory in which data of a memory cell can be renewed by a byte unit.
2. Description of the Related Art
An EEPROM is known as a nonvolatile semiconductor memory in which data of a memory cell can be renewed by a byte unit. For example, for a floating gate tunnel oxide (FLOTOX) cell disclosed in Non-patent Document 1, the data of the memory cell can be renewed by the byte unit.
FIG. 1 is a plan view of a FLOTOX cell, and FIG. 2 is a sectional view along line II-II of FIG. 1. The characteristics of the cell lie in that a thin oxide film 22a having a thickness of about 10 nm referred to as a tunnel oxide film exists on an N+ drain region 20a. When a high electric field is generated between the drain region 20a and a control gate electrode 23a, charges are exchanged between the drain region 20a and a floating gate electrode 21a via a tunnel oxide film.
FIG. 3 shows a band structure of a portion of the tunnel oxide film 22a of FIGS. 1 and 2. As apparent from this figure, when the high electric field is generated between the drain region 20a and control gate electrode 23a, a Fowler-Nordheim (FN) tunnel current flows through the tunnel oxide film 22a according to Equation (1):I=SaE2 exp(−a/E)  (1),wherein S denotes an area of the tunnel oxide film, and E denotes the electric field.
                                              ⁢                  =                      q            ⁢                                                  ⁢                          3              /              8                        ⁢                                                  ⁢                          nh              (                              DB                =                                                      6.94                    ×                    10                                    -                                      7                    ⁡                                          [                                              A                        /                        V2                                            ]                                                                                                                                  =                              -            4                    ⁢                      (                          2              ⁢                                                          ⁢              m                        )                    ⁢          0.5          ⁢                      (                          DB              ⁢                                                          ⁢                              1.5                /                3                            ⁢                                                          ⁢              hq                                                              =                  2.54          ×                      108            ⁢                                                  [                          V              ⁢                              /                            ⁢              cm                        ]                              
According to this equation, it is seen that an FN tunnel current starts to flow in an electric field of about 10 MV/cm. This intensity of the electric field corresponds to a case in which a voltage of about 10V is applied to the tunnel oxide film having a thickness of about 10 nm.
Here, assuming that a ratio of capacities of the floating gate electrode 21a and control gate electrode 23a to those of the floating gate electrode 21a and surrounding electrode wiring, that is, a coupling ratio is 0.5, in order to obtain a potential difference of 10V between the floating gate electrode 21a and drain region 20a, for example, the drain region 20a needs to be set to 0V, and the control gate electrode 23a needs to be set to 20V. At this time, electrons in the drain region 20a are injected into the floating gate electrode 21a. 
Moreover, when the coupling ratio is 0.5, in order to obtain a potential difference of 10V between the floating gate electrode 21a and drain region 20a, for example, the drain region 20a needs to be set to 20V, and the control gate electrode 23a needs to be set to 0V. At this time, the electrons in the floating gate electrode 21a are discharged into the drain region 20a. 
The memory cell using the FLOTOX cell cannot be constituted of only one element of the FLOTOX cell. This is because a reverse bias applied to a nonselected memory cell at an erase time generates a write state. That is, to solve this problem, for example, one memory cell has to be constituted of a circuit shown in FIG. 4. Bias conditions in each mode of EEPROM using the memory cell shown in FIG. 4 are shown in Table 1.
TABLE 1Non-selectedbyteNon-selectedconnected tobytethe sameconnected toword line asthe same bitthat ofline as thatSelectedselectedof selectedModebytebytebyteEraseWordHighHighLow(“0”linewrite)ByteHighLowHighcontrolBitLowLowLowline“1”WordHighHighLowWritelineByteLowLowLowcontrolBitHigh orLowHigh orlineLow*1Low*2*1= Data dependent*2= Don't care
This memory cell is a novel circuit in which various disturbances can completely be removed by a selected transistor ST and transfer gate Tr, but the number of transistors per memory cell is 2+(⅛) transistors, and there is a problem that a memory cell size increases. The tunnel oxide film needs to be disposed in a region separate from that in which a cell transistor is formed, and this causes cost increase.
The nonvolatile semiconductor memory developed to avoid this problem is a flash memory (EEPROM). In a related-art EEPROM, it is possible to erase and write the data every bit, and the EEPROM is very easy to use. However, for example, for a hard disk, the data does not have to be renewed every bit, and the hard disk suffices, if the data can be exchanged by a sector unit, that is, by a unit of one group of a plurality of bits.
It is necessary not to renew the data every bit, but to provide an inexpensive nonvolatile semiconductor memory. From this idea, a flash memory has been developed as described in Non-patent Document 2.
A basic structure of the memory cell is the same as that of an ultraviolet erase type EPROM as shown in FIG. 5. That is, the floating gate electrode is disposed between the control gate electrode and silicon substrate (channel) of MOS transistor. The write is performed by injection of hot electrons in the same manner as in the ultraviolet erase type EPROM, and the erase is performed by discharge of the electric field from the floating gate electrode in the same manner as in a byte type EPROM.
An erase principle of the flash memory is the same as that of the byte type EEPROM, but the entire structure is totally different from that of the byte type EEPROM. That is, in the byte type EEPROM, the data is erased by a byte unit. However, for the flash memory, in principle, all the bits are collectively erased.
Moreover, as described above, the data is written in the flash memory by the hot electron injection in the same manner as in the ultraviolet erase type EPROM, and it is therefore possible to write the data every bit. That is, concerning a write/erase operation, for the flash memory, all the bits are collectively erased, and this is the same as in the ultraviolet erase type EPROM in which the data is written every bit by the hot electron injection.
Furthermore, an NAND type flash memory has been proposed as a flash memory which can highly be integrated as described in Non-patent Document 3.
For example, as shown in FIGS. 6 and 7, a memory cell array of the NAND type flash memory is constituted of an NAND cell unit. The NAND cell unit is constituted of a cell array including a plurality of (e.g., 16) memory cells connected in series, and two select gate transistors disposed in opposite ends of the cell array.
In the NAND type flash memory, only one bit line contact portion and only one source line contact portion may be disposed with respect to one NAND cell unit, and this can contribute to reduction of a memory cell size per bit and further to the reduction of a chip size. For example, in the NAND type flash memory, the chip size can largely be reduced as compared with an NOR type flash memory (FIG. 8) in which the memory cells only for one bit are disposed between the bit line and source line.
In this manner, the NAND type flash memory has maximum features of a large-capacity file memory, in which the chip size is small and a bit cost is small. Also for the function of the NAND type flash memory, as compared with the NOR type flash memory, there are features that renewal speed of the data is fast and that power consumption is small.
The features that the renewal speed of the data is fast and that the power consumption is small are realized by a data renewal system peculiar to the NAND type flash memory. This peculiar data renewal system comprises: using an FN tunnel current to discharge/charge electric charges between the silicon substrate and floating gate electrode and to write and erase the data.
Therefore, considering only the memory cell, in principle, the current necessary for the write is only the FN tunnel current with respect to only the floating gate electrode. That is, the power consumption at a write time is largely reduced as compared with the NOR type flash memory by the hot electron injection. Therefore, even when the data is simultaneously written with respect to a plurality of bits, the power consumption hardly increases.
For example, with a 64 megabit NAND type flash memory, it is possible to write the data by a unit of one page (512 bytes) at 200 μs. In this manner, for the NAND type flash memory, as compared with the NOR type flash memory, there are features that a renewal time by one block unit is very short and that the power consumption necessary for the renewal is also small.
Table 2 shows the features of the NAND type flash memory in comparison with those of the NOR type flash memory.
TABLE 2NANDNORAdvantage(1) Write speed is(1) Random access isfastfast(2) Erase speed is(2) Write isfastpossible at random(3) Block size isevery bytesmall and file iseasily managed.Disadvantage(1) Random access(1) Write speed isis slowslow(2) Write is not(2) Erase speed ispossible every byteslowUseReplacement of hardReplacement ofdisk and floppyrelated-art EPROMdisk, portablefield, controlterminal (handyapparatus, BIOS ofterminal, soundPC, cellular phone,recording,memories for controlelectronic stillsuch as HDDcamera) Fax/modemdata recording
As shown in Table 2, advantages and disadvantages of both the memories are in a mutual complementary relation. For example, concerning use, the NAND type flash memory is used in a field in which the data is renewed/read by a specific block data unit. For example, in a digital camera including 300,000 pixels, since a photograph of one shot requires a storage capacity of about 0.5 megabits, the NAND type flash memory has broadly been used for data storage.
On the other hand, the NOR type flash memory has broadly been used as a memory for control program of a cellular phone, because a random access is possible at a high rate of 100 ns.
In this manner, in a field of the nonvolatile semiconductor memory, the memory has evolved into the EEPROM (related-art type), flash memory, and NAND type flash memory. Instead of a renewal function by the byte unit, the reduction of the memory cell size, that is, the reduction of cost per bit (bit cost) has been achieved.
However, in recent years, there has been a rising demand for the data renewal by the byte unit in a logic embedded nonvolatile memory. For example, in an IC card, when a part of the data is renewed in management of moneys such as income and expenditure, with the use of the flash memory, the amount of data to be renewed becomes excessively large.
Therefore, to eliminate these disadvantages, a byte type EEPROM is required in which the renewal is possible by the byte unit. Additionally, the byte type EEPROM has a problem that the number of elements per bit, that is, a cell area is large as described above. At present, mainstream of the nonvolatile semiconductor memory has been the flash memory (NOR type, NAND type, and the like). Therefore, with the same process as that of the memory, a development cost and production cost can be reduced.
Under these situations, at present, a nonvolatile semiconductor memory has been developed which can be formed by the same process as that of the flash memory and in which the same data renewal system as that of the flash memory can be used and in which the renewal by the byte unit is also possible (e.g., see Patent Documents 1 to 5).
Particularly, the nonvolatile semiconductor memory described in Patent Document 3 is referred to as so-called 3Tr. NAND, and will be noticed as a memory embedded with the logic circuit or the NAND type flash memory. The memory cell of 3Tr. NAND is constituted of three transistors in total including one cell transistor and two select gate transistors between which the cell transistor is held.
In 3Tr. NAND, for example, to renew the data with respect to an arbitrary memory cell in memory cells for one page connected to a selected control gate line, a method is used comprising: (1) reading the data of the memory cells for one page into a sense amplifier; (2) erasing the page; (3) overwriting only the data to be renewed in the one page data in a sense amplifier; and thereafter (4) rewriting the data with respect to the memory cell for one page.
This is the renewing by the byte unit as seen from the outside of a chip. However, when seen from the inside of the chip, also for the data which is not to be renewed, the cell data is once erased by page erase. That is, with occurrence of an operation defect or an erroneous operation in the sense amplifier in which the cell data is temporarily stored, there is a possibility that the data not to be renewed turns to wrong data.
Needless to say, since an error correction circuit (ECC) is disposed in the chip to enhance reliability, the situation can be handled by the ECC in any case, but if there is not such fear, that would be the best possible thing.
Patent Document 1: Jpn. Pat. Appln. KOKAI Publication No. 11-195718
Patent Document 2: Jpn. Pat. Appln. KOKAI Publication No. 11-297081
Patent Document 3: Jpn. Pat. Appln. KOKAI Publication No. 2000-149581
Patent Document 4: Jpn. Pat. Appln. KOKAI Publication No. 2002-43444
Patent Document 5: U.S. Pat. No. 4,636,984
Non-patent Document 1: W. Johnson et al., “A 16 Kb Electrically Erasable Nonvolatile Memory,” ISSCC Digest of Technical Papers, pp. 152 and 153, February 1980
Non-patent Document 2: F. Masuoka et al., “A new Flash EEPROM cell using triple polysilicon technology,” IEDM Technical Digest, pp. 464 to 467 December 1984.
Non-patent Document 3: F. Masuoka et al., “New ultra high density EPROM and Flash EEPROM with NAND structured cell.” IEDM Technical Digest, pp. 552 to 555 December 1987.